Item – Theses Canada

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OCLC number
67856000
Link(s) to full text
LAC copy
LAC copy
Author
Jin, Huang,1974-
Title
An embedded DRAM memory architecture and its prototype implementation in programmable logic.
Degree
M. Sc.(Eng) -- Queen's University, 2004
Publisher
Ottawa : Library and Archives Canada = Bibliothèque et Archives Canada, [2005]
Description
2 microfiches.
Notes
Includes bibliographical references.
Abstract
The continued scaling of CMOS technology down to feature sizes of 0.13[mu]m and below makes it feasible to embed large amounts of dynamic random access memory (DRAM) on the same die with logic components in System-on-Chip designs. This paradigm provides wide on-chip memory interfaces, low power consumptions and customized memory capacities, all of which are very attractive to multimedia and network applications. Embedding DRAM components not only provides a new design dimension in large-scale integration, but also presents challenges in system-level redesigns of memory architecture in order to obtain optimal memory performance. This thesis describes an embedded DRAM architecture and its prototype implementation in programmable logic. It intends to explore the design space in implementation to complement previous simulation-based memory research. The investigation is focused on the memory interface, the memory bank organization and the memory control schemes. The first contribution of this thesis is the design of an embedded DRAM architecture to achieve reduced average access latency. The second contribution is the prototype implementation for the proposed architecture in programmable logic. (Abstract shortened by UMI.)
ISBN
061299869X
9780612998698